Towards a Practical Design Methodology with SystemVerilog Interfaces and Modports
نویسنده
چکیده
Explores the benefits and limitations of SystemVerilog interfaces and modports in block-level design. Identifies key problems of portability, re-use and flexibility in interface-based design, and suggests a methodology for adoption of SystemVerilog interfaces and modports that helps to solve these problems in synthesizable designs.
منابع مشابه
SystemVerilog: Interface Based Design
After establishing of various possibilities of abstraction in HDLs (on values, time, and structure) many years ago, SystemVerilog as a combined HDVL offers a new approach to support also abstraction on ports. This interface concept extends the feasibilities for encapsulation when designing, connecting, and verifying the numerous interfaces in modern SoC designs. This can be done on an abstract,...
متن کاملEasier SystemVerilog with UVM: Taming the Beast
SystemVerilog has been widely adopted as a language for hardware design and verification. At the same time, SystemVerilog is a very large and complex language which can be daunting to learn and use, and differences still remain between implementations. SystemVerilog adoption has been given a new impetus in recent years with the introduction of UVM, the Universal Verification Methodology for Sys...
متن کاملSystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces
This paper describes how to model channel-based digital asynchronous circuits using SystemVerilog interfaces that implement CSP-like communication events. The interfaces enable explicit handshaking of channel wires as well as abstract CSP events. This enables abstract connections between modules that are described at different levels of abstraction facilitating both verification and design. We ...
متن کاملAsynchronous Behaviors Meet Their Match with SystemVerilog Assertions
Most digital designs inherently possess asynchronous behaviors of some kind. While the SystemVerilog assertion (SVA) language offers some asynchronous controls like disable iff, writing concurrent assertions that accurately describe asynchronous behavior is not so straightforward. SVA properties require a clocking event, making them innately synchronous. When describing asynchronous behavior, t...
متن کاملSystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got Easier
The OVM and VMM methodologies each provide powerful, flexible and intuitive frameworks for the construction of SystemVerilog verification environments. However, many SystemVerilog users also have models written in C, C++, or sometimes SystemC. Furthermore, the emergence of the SystemC TLM-1 and TLM-2.0 transaction-level modeling standards is having an impact on communication styles within Syste...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2007